In the packaging of integrated circuits, dies may be packaged onto other package components such as package substrates, interposers, printed circuit boards (PCBs), or the like. The packaging may be performed through flip chip bonding.
Since the coefficients of thermal expansion (CTE) of the dies and the CTEs of different package components may be significantly different from each other, after the flip chip bonding is performed, a significant stress may be generated in the resulting package. The stress may also be applied on the dies and other package components in the respective packages. With the increase in the sizes of the dies and the package components, the stress may be further increased, and hence a more significant problem has been observed in recent manufacturing processes, in which larger dies are used. Typically, the stress is highest at the corners of the dies because the corners have the highest distances to neutral points (DNP). The stress may cause solder cracking, dielectric cracking, and/or delamination between the dielectric layers in the dies, especially when lead-free solder is used in the package. The cracks and the delamination may propagate to other parts of the dies, causing circuit failure.
Various solutions were proposed to solve the problem caused by the high stress. In some solutions, since the corner bumps are most likely to have stresses, the structures adjacent to the corner bumps are enhanced. In some other solutions, the corner bumps are designed as dummy bumps, which are not used for electrical connection. Instead, the dummy corner bumps are used for absorbing the stresses.